CSCE 434 Lecture 38
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Optimal Code Generation
- Loading from memory takes extra cycles.
- Regular instructions take 1 cycle
If CPU is caught up waiting for memory access, we call this state interlock
Interlocking (occurs when ) wastes resaurces because nothing is being done while we wait for data
Solution: move loads to be executed as early as possible before they are used:
- Load
- Do stuff that doesn't depend on while is being loaded
- this section should be at least cycles long
- Puts pressure on competition for registers: make sure we don't use the register that is reserved for
- Need to minimize this pressure
- Use
Phase Ordering
- Allocate first and then schedule instructions → poor scheduling
- Schedule first and then allocate → poor allocation
Consider two problems simultaneously.
Legal ordering:
- children of an operator appear before it (i.e. preserve ordering between operations)
- each load occurs before the operation that uses it (i.e. preserve ordering between loads)
DLS Algorithm
- Run Sethi-Ullman algorithm
- Calculate for each subtree
- create ordering of operations
- Put loads into canonical order
- Uses regs
- Requires some renaming
Canonical order
Given registers,
- Schedule loads
- Schedule series of op/load pairs
- Schedule remaining operations
Code Generator Generators
Like bison for machine code
Remember the name Berton Smith: Tera Computers.
Two approaches:
- Tree-matching
- Instruction-matching
Table-Driven code generator reads machine-specific table produced by a code generator generator
Example pattern:
When you see r = + a b
, emit load r1, a; load r2, b; add r1 r2;
Tree Parsing
Use LR Parsers
- Encode pattern matching as parsing problem
- reductions emit code instead of producing AST
- BUT: grammars are very ambiguous
Instruction Matching
Peephole optimization: very narrow field of view
Compiler Design Philosophy
Spend time (and money) in
- Optimize
- Schedule
- Allocate